Group iii-v compound transistor



May 23, 1967 D. w. FLATLEY ET AL. 3,321,682

GROUP IIIV COMPOUND TRANSISTOR 5 Sheets-Sheet l Original Filed May 20,1965 Ffyff'.

fm/e/z fors.-

/hfamel/ May 23, 1967 D. W. FLATLEY ETAL GROUP IIIV COMF'OUND TRANSISTORoriginal Filed May 20, 1963 5 Sheets-Sheet 2 I far/zelf May 23, l967 D.w. FLATLEY ETAL I 3,321,682

GROUP III-V COMPOUND TRANSISTOR Original Filed May 20, 1963 5Sheets-Sheet 5 United States Patent Uffice -ZLGSZ Patented May 23, 19673,321,682 GROUP III-V CMPOUND TRANSISTOR Doris W. Flatiey, Trenton, HausW. Beeke, Morristown, and Daniel Stolnitz, Raritan, NJ., assignors toRadio Corporation of America, a corporation of Delaware Originalapplication May 20, 1963, Ser. No. 281,559, new Patent No. 3,255,056.Divided and this application Apr. 14, 1%6, Ser. No. 542,573

2 Claims. (Ci. 317-237) This application is a division of applicationSer. No. 281,559, now Patent No. 3,255,056, filed May 20, 1963, Thisinvention relates to improved semiconductor devices and improved-methods of fabricating them.

It is known that in addition to the conventional elementalsemiconductors such as germanium and silicon, certain crystallinecompounds may also be utilized Ias semiconductors in the fabrication ofjunction devices. One such group of 4compounds consists of an element`from Group III of the Periodic Table combined with an element fromGroup V of the Periodic Table, and are therefore known as the III-Vcompounds. Examples of such compound semiconductors are the phosphides,larsenides and antimonides of boron, aluminum, gallium and indium. For adetailed description of these semiconductive materials and theirproperties, see for example Willardson and Goering, CompoundSemiconductors, vol I, Preparation of III-V Compounds, ReinholdPublishing Co., New York, 1962. Some of these compounds, such as galliumphosphide, have an energy gap which is too high, and others, such asindium antimonide, have an energy gap which is too low for generaldevice applications. The III-1V compounds regarded as most suitable fordevices which include a reotifying barrier are indium phosphide andgallium arsenide.

The techniques described herein for fabricating transistors from theIII-IV compounds result in an extremely narrow 'base region.Consequently, la large portion of charge carriers injected from theemitter region into the base of the transistor so fabricated survivelong enough to diffuse through the base region and reach thebase-collector junction. Another advanatge of these techniques is thatthe resulting transistors have a high ra-tio of conductivity of emitterregion to conductivity of ibase region, for ex-ample, a ratio of about20 to 1 at room temperature (that is, at about 20 C.) These advantagesare evidenced by improved operating characteristics in such III-Vtransistors. However, the invention may also be employed in fabricatingtransistors other than those of the III-IV `compound group.

Accordingly, it is an object of this invention to provide improvedmethods of fabricating improve-d semiconductor devices.

Anoher object is to provide improved semiconductor devices.

Still another object is to provide III-V compound transistors having avery thin base region.

But Vanother object is to provide III-V compound transistors having ahigh ratio of e-mitter region conductivity to base region conductivity.

These and other objects and advantages are obtained by an improvedcombination of in-diffusion and out-diffusion techniques which providesa semiconductor device comprising a =wafer of a crystallinesemiconductive material such as III-V semiconductive compound. Thecompound is preferably selected from the group consisting of galliumarsenide and indium phosphide. The wafer includes a P-conductivity typeregion less than one micron thick. The P-type region has a net excess ofzinc atoms over N-type impurities of less than 5 X101Y zinc atoms percm3.

The invention will .be described in greater detail by the followingexample, considered in conjunction with the accompanying drawing, inwhich:

FIGURES 1-14 are cross-sectional schematic views of a wafer duringsuccessive steps in the fabrication of a semiconductor device; and

FIGURE 15 is a liow sheet of certain steps of one ernbodiment of aprocess of manufacture of a device, in accordance with the invention.

Example A semiconductor wafer 10 (FIGURE 1) of one of the crystallinesemiconductive III-V compounds is prepared with at least one major waferface 11. The semiconductive material is preferably selected from thegroup consisting of indium phosphide and gallium arsenide. In thisexample, wIafer 10 consists of monocrystalline gallium arsenide. Theexact size Iand shape of wafer 10 is not critical. In this example,Wafer 10 is about 40 mils square and 7 mils thick. The semiconductivewafer may ybe of either conductivity type, or intrinsic or compensated.In this example, Wafer 10 is of N-type conductivity. A layer 12 of aninsulating oxide such as silicon oxide, titanium oxide, and the like isnow deposited on major Wafer face 11 by any convenient method. In thisexample, insulating layer 12 consists of silicon oxide, and is`deposited by thermally decomposing a siloxane compound, and passing thevaporized decomposition products of the siloxane compound over thewafer. The -layer 12 is suitably about 1000 to 10,000 Angstroms thick.

Referring now to FIGURE 2, a substance which is a conductivity modifierin III-V compounds is diffused into the silicon oxide layer 12 only. Theextent and concentration of the modifier is indicated qualitatively bythe dotted Iareas 13 in FIGURES 2-7. In FIGURES 8-15, the extent andconcentration of the modifier is omitted for greater clarity, since itis the same as in FIGURE 7. In this example, the conductivity modier iszinc. Wafer 10 is heated to about 725 C. in a non-oxidizing ambient suchas argon in the presence of a source of zinc vapors for a period of time(about 4 minutes has been found suitable) suiiicient to diffuse some ofthe conductivity modiiier 13 (zinc in this example) into the siliconoxide layer 12. However, the temperature and time of this heating stepIare insufficient for the modifier to ditfuse completely through thesi-licon oxide layer 12 and into the lwafer 10. The modifier 13 thusremains concentrated in the uppermost portion of the first silicon oxidelayer 12, that is, the portion which is not immediately adjacent waferface 11.

Referring now to FIGURE 3, wafer 10 is reheated in a non-oxidizingambient which is free from any conductivity modifiers. The time andtemperature of this heating step are selected so that the conductivitymodifier in the silicon oxide layer 12 diffuses completely through thesilicon oxide layer 12 and a short distance (only about 0.4 micron) intothe wafer 10. In this example, wafer 10 is heated to about 800 C. forabout 4 hours. The zinc diffused wafer region 14 is converted to P-typeconductivity, and a rectifying barrier or PN junction 15 is formedbetween the P-type zinc diffused region 14 immediately adjacent thesilicon oxide layer 12 and the N-type bulk of wafer 10.

The first silicon oxide layer 12 is now removed, leaving the wafer 10 asillustrated in FIGURE 4. The silicon oxide layer 12 may be convenientlyremoved by etching in concentrated hydrouoric acid, or in an etchantcontaining hydrouoric acid.

Referring now to FIGURE 5, a second silicon oxide layer 22 is depositedon face 11 of wafer 10. The second silicon oxide layer 22 may bedeposited in the same manner as the first silicon oxide layer 12, or byany other convenient technique.

Wafer 10 is reheated in a non-oxidizing ambient. In this example, thegallium arsenide wafer 10 is reheated in argon at about 900 C. for about24 hours. The effect of this heating step is to diffuse some of theconductivity modifier (zinc in this example) outward from region 14 intothe second silicon oxide layer 22, as illustrated in FIGURE 6. At thesame time, some of the conductivity modifier diffuses deeper into thewafer, thus making the P-type region in the wafer thicker. As a resultof this combination of out-diffusion and in-diffusion, the concentrationof the conductivity modifier in the P- type region is decreased, and inparticular the concentration of the modifier on the surface 11 of wafer10 is sharply decreased. The net excess of zinc atoms over N- typeimpurities at the surface of the wafer is thereby reduced to less than5X 1017 zinc atoms per cm3. In this example, the thicker and lessheavily doped P-type region of wafer is denoted by reference numeral 14in FIG- URE 6. The PN junction that is formed is deeper into wafer 10than the previous PN junction 15, as a result of this step, and isdenoted by reference numeral in FIGURE 6. Region 14' is only about 0.8micron thick in this example.

Preselected portions of silicon oxide layer 22 are removed by anyconvenient method, such as photolithographic techniques, and theremainder of layer 22 is utilized as a diffusion mask. The silicon oxidelayer 22 is coated with film 23 (FIGURE 7) of a photoresist, which maybe a bichromated protein such as bichromated albumen, bichromated gumarabic, and the like. Commercially available photosensitive resists,such as KPR, manufactured by the Eastman Kodak Company; CFC;manufactured by the Clerkin Company; and Hot Top,

Vmanufactured by the Pitman Company, may also be utilized for thispurpose.

The photoresist film 23 is suitably masked; the unmasked portions of thephotoresist are exposed to light and thus polymerized and hardened; theunexposed portions of the photoresist are removed with a suitableorganic solvent such as xylol and the like; and the portion of siliconoxide layer 22 thus exposed is removed by an etchant. An aperture 24(FIGURE 8) which defines a portion, which may be a circular portion, ofwafer face 11 is thereby formed in the silicon oxide layer 22.

Referring now to FIGURE 9, the remaining portion of photoresist film 23is removed by means of a suitable stripper such as methylene chloride orthe like, and the wafer 10 is then heated in an ambient comprising asubstance which is a conductivity modifier in yIII-V compounds. In thisexample, the conductivity modifier is tin. Tin is an N-type conductivitymodifier in III-V cornpounds such as gallium arsenide. Since galliumarsenide tends to dissociate when heated and emit arsenic vapors, thewafer 10 is preferably heated in an ambient containing a vapor pressureof arsenic which is greater than the pressure of arsenic produced by thedissociation of gallium arsenide at the temperature utilized, therebypreventing the wafer from losing arsenic. In this example,

f wafer 10 is heated to about 950 C. for a period of about 10 to 60minutes in an ambient containing sufficient arsenic vapors to exhibit apartial pressure of about 0.5 atmosphere. Y As a result of thisdiffusion step, sufficient tin diffuses into the exposed portion ofwafer face 11 to form an N-type wafer region 16. Wafer region 16 isabout 0.4 micron thick in this example, and is completely surrounded bythe zinc-diffused P-type wafer region 14. A rectifying barrier or PNjunction 17 is formed at the interface between N-type wafer region 16and P-type wafer region 14.

The remaining portions of silicon oxide layer 22 are now removed bylapping or grinding, or by means of a suitable etchant such asconcentrated hydrofluoric acid, leaving wafer 10 with two rectifyingbarriers 15 and 17 as illustrated in FIGURE l0. A third silicon oxidelayer 32 (FIGURE ll) is now deposited on wafer fa-ce 11. Utilizing thephotolithographic techniques described above portions of silicon oxidelayer 32 are removed, leaving a central aperture 44 completely Withinthe tindiffused region 16, and a surrounding annular aperture 43 whichis completely within the zinc-diffused P-type region 14.

Referring now to FIGURE l2, a metallic film 45 is depositioned by anyconvenient method, such as evaporation, over the silicon oxide layer 32and also over the exposed portions of wafer face 11 within apertures 43and 44. The metallic film 45 may for example consist of silver,chromium, gold, or the like. The portions of metallic film 45 which arenot on the wafer surface are then removed by conventional masking andetching techniques. Wafer 10 is heated in a non-oxidizing ambient suchas hydrogen to alloy the remaining portions of film 45 to the wafer. Ametallic contact 18 (FIGURE 13) is thus formed to N-type region 16, andanother metallic Contact to P-type region 14'. A central portion ofwafer face 11 including electrodes 18 and 19 is then covered with asuitable resist 46, which may for example `consist of paraffin wax orapiezon wax. The opposite major face of wafer 10 is similarly protectedby the acid resist 46.

Wafer 10 is then immersed in a suitable etchant, so as to remove asurface portion of the wafer except for that part of the wafer masked byresist 46. A mesa 20 (FIG- URE 14) is thus formed on the wafer. Thewafer is removed from the etchant, washed, and the resist 46 removed bya suitable solvent. The remaining steps of attaching lead wires tocontacts 18 and 19, and mounting and encapsulating the device, areaccomplished by any of the suitable techniques known to thesemiconductor art, and need not be described here. In operating thedevice as an NPN transistor, the region 16 serves as the emitter region,the region 14' serves as the base region, and the remainder of wafer 10is the collector region.

In the devices fabricated according to the invention, the effectiveconcentration of tin atoms (donor atoms) in the emitter region is about1X 1019 tin atoms per cm3, while the concentration of zinc atoms(acceptor atoms) at the surface of the base region is less than 5 1017zinc atoms per cm3. A favorable ratio of emitter conductivity to baseconductivity is thus obtained, which results in useful injectionefficiency. Moreover, the thickness of the P-type base region 14 in thedevices thus fabricated is not only much less than hitherto obtainable,being only about 0.4 micron thick between the emitter and collectorregions, but is also very uniform and reproduceable, and thereforesuitable for mass production. Galliurn arsenide transistors fabricatedin accordance with this example exhibited power gains of about l2 db ata frequency of 50 megacycles. It was also unexpectedly found that theelectrical characteristics of the units thus fabricated remainedsurprisingly stable over the temperature range from 4 K., thetemperature of liquid helium, to 570 K.

A preferred form of the invention has thus been described by way ofillustration only, and not limitation. Other crystalline semiconductivematerials may be utilized for the wafer. Other conductivity modifiersfor III-V compounds, such as cadmium, selenium, tellurium, and the like,may be utilized. Although the device of the example was an NPN typetransistor, the conductivity types of the various regions may bereversed, utilizing known acceptors and donors, so as to fabricatecorresponding PNP type transistors. The shapes of the emitter and basecontacts may be altered as desired, for example to form the emitter andbase contacts in the shape of two closely adjacent rectangles, or withirregular outlines to increase the periphery of the contacts withoutincreasing their total area. It will be understood that various changesand modifications may be made by those skilled in the art withoutdeparting from the spirit and scope of the invention as defined in thespecification and the appended claims.

We claim:

1. A transistor comprising:

an N type crystalline semiconductive body having at least one majorface, said body consisting of a material selected from the groupconsisting of the phosphides, arsenides and antimonides of boron,aluminum, gallium and indium;

a P type base Zone in said body immediately adjacent said major face,said zone being about 0.4 micron thick and containing a net excess ofZinc atoms over N type impurity atoms, said excess being less than 51017 zinc atoms -per cm.3 at said one major face;

a rectifying barrier between said P type zone and said N type body;

an N type emitter region in said body immediately adjacent said oneface, said N type region being completely surrounded by said P typezone, the concentration of donor atoms in said emitter` region beingabout 1 1019 atoms per cm.

a rectifying barrier between said N type emitter region and said P typebase Zone;

a metallic contact to said N type emitter region;

Va metallic Contact to said P type base zone; and,

electrical connections to said contacts.

2. A transistor as in claim 1, wherein said body consists of galliumarsenide.

References Cited by the Examiner UNITED STATES PATENTS 3,060,327 10/1962Dacey 307-885 3,131,096 4/1964 Sommers 418-33 OTHER REFERENCESSemiconductors, edited by N. B. Hanney, copyright 1959 by ReingoldPublishing Corp., N.Y., Patent Oice Scientic Library #QC612S4H32-c.5.,pages 405-09 containing article by I. M. Whelan, Properties of SomeCovalent Semiconductors.

S. W. Ing, Ir., and H. A. Jensen: Light-Coupled Negative-ResistanceDevice in GaAs, from Proceedings of the IEEE, vol. 51, No.5, May 1963,page 851.

JOHN W. HUCKERT, Primary Examiner.

A. M. LESNIAK, D. O. KRAFT, Assistrm't Examiners.

1. A TRANSISTOR COMPRISING: AN N TYPE CRYSTALLINE SEMICONDUCTIVE BODYHAVING AT LEAST ONE MAJOR FACE, SAID BODY CONSISTING OF A MATERIALSELECTED FROM THE GROUP CONSISTING OF THE PHOSPHIDES, ARSENIDES ANDANTIMONIDES OF BORON, ALUMINUM, GALLIUM AND INDIUM; A P TYPE BASE ZONEIN SAID BODY IMMEDIATELY ADJACENT SAID MAJOR FACE, SAID ZONE BEING ABOUT0.4 MICRON THICK AND CONTAINING A NET EXCESS OF ZINC ATOMS OVER N TYPEIMPURI-TY ATOMS, SAID EXCESS BEING LESS THAN 5X10**17 ZINC ATOMS PERCM.3 AT SAID ONE MAJOR FACE; A RECTIFYING BARRIER BETWEEN SAID P TYPEZONE AND SAID N TYPE BODY; AN N TYPE EMITTER REGION IN SAID BODYIMMEDIATELY ADJACENT SAID ONE FACE, SAID N TYUPE REGION BEING COMPLETELYSURROUNDED BY SAID P TYPE ZONE, THE CONCENTRATION OF DONOR ATOMS IN SAIDEMITTER REGION BEING ABOUT 1X10**19 ATOMS PER CM.3; A RECTIFYING BARRIERBETWEEN SAID N TYPE EMITTER REGION AND SAID P TYPE BASE ZONE; A METALLICCONTACT TO SAID N TYPE EMITTER REGION; A METALLIC CONTACT TO SAID P TYPEBASE ZONE; AND, ELECTRICAL CONNECTIONS TO SAID CONTACTS,